00001 /* ---------------------------------------------------------------------- 00002 * Copyright (C) 2010 ARM Limited. All rights reserved. 00003 * 00004 * $Date: 15. July 2011 00005 * $Revision: V1.0.10 00006 * 00007 * Project: CMSIS DSP Library 00008 * Title: arm_biquad_cascade_df1_init_q31.c 00009 * 00010 * Description: Q31 Biquad cascade DirectFormI(DF1) filter initialization function. 00011 * 00012 * 00013 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 00014 * 00015 * Version 1.0.10 2011/7/15 00016 * Big Endian support added and Merged M0 and M3/M4 Source code. 00017 * 00018 * Version 1.0.3 2010/11/29 00019 * Re-organized the CMSIS folders and updated documentation. 00020 * 00021 * Version 1.0.2 2010/11/11 00022 * Documentation updated. 00023 * 00024 * Version 1.0.1 2010/10/05 00025 * Production release and review comments incorporated. 00026 * 00027 * Version 1.0.0 2010/09/20 00028 * Production release and review comments incorporated. 00029 * 00030 * Version 0.0.5 2010/04/26 00031 * incorporated review comments and updated with latest CMSIS layer 00032 * 00033 * Version 0.0.3 2010/03/10 00034 * Initial version 00035 * -------------------------------------------------------------------- */ 00036 00037 #include "arm_math.h" 00038 00081 void arm_biquad_cascade_df1_init_q31( 00082 arm_biquad_casd_df1_inst_q31 * S, 00083 uint8_t numStages, 00084 q31_t * pCoeffs, 00085 q31_t * pState, 00086 int8_t postShift) 00087 { 00088 /* Assign filter stages */ 00089 S->numStages = numStages; 00090 00091 /* Assign postShift to be applied to the output */ 00092 S->postShift = postShift; 00093 00094 /* Assign coefficient pointer */ 00095 S->pCoeffs = pCoeffs; 00096 00097 /* Clear state buffer and size is always 4 * numStages */ 00098 memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q31_t)); 00099 00100 /* Assign state pointer */ 00101 S->pState = pState; 00102 } 00103